//*******************************************************************
`define U_DLY 1
`timescale 1ns/1ps
module axi4_s_fifo
#(
parameter WIDTH = 8 ,
parameter DEPTH_D = 4
)
(
input clk ,
input rst_n ,
output reg s_axis_tready ,
input s_axis_tvalid ,
input [WIDTH-1:0 ] s_axis_tdata ,
input m_axis_tready ,
output reg m_axis_tvalid ,
output reg [WIDTH-1:0 ] m_axis_tdata
);
localparam DEPTH_W = $clog2(DEPTH_D) ;
localparam DEPTH_D_1 = DEPTH_D – 1 ;
wire ram_wren ;
wire [DEPTH_W-1:0] ram_wadr ;
wire [WIDTH-1:0 ] ram_wdat ;
wire ram_rden ;
wire [DEPTH_W-1:0] ram_radr ;
wire [WIDTH-1:0 ] ram_rdat ;
reg [DEPTH_W:0 ] cnt_data ;
reg [DEPTH_W-1:0] wr_addr ;
reg rden_reg ;
reg [DEPTH_W-1:0] rd_addr ;
reg m_tvalid ;
reg m_tvalid_reg ;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt_data <= #`U_DLY ‘d0 ;
else if( (s_axis_tready&&s_axis_tvalid) && (!rden_reg) )
cnt_data <= #`U_DLY cnt_data + 1’b1 ;
else if( (!(s_axis_tready&&s_axis_tvalid)) && (rden_reg) )
cnt_data <= #`U_DLY cnt_data – 1’b1 ;
else keep
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
s_axis_tready <= #`U_DLY 1’b0 ;
else if( (cnt_data==DEPTH_D_1) && (s_axis_tready&&s_axis_tvalid) && (!rden_reg) )
s_axis_tready <= #`U_DLY 1’b0 ;
else if(cnt_data==DEPTH_D)
s_axis_tready <= #`U_DLY 1’b0 ;
else
s_axis_tready <= #`U_DLY 1’b1 ;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
wr_addr <= #`U_DLY ‘d0 ;
else if(s_axis_tready&&s_axis_tvalid)
wr_addr <= #`U_DLY wr_addr + 1’b1 ;
else keep
end
assign ram_wren = s_axis_tready & s_axis_tvalid ;
assign ram_wadr = wr_addr ;
assign ram_wdat = s_axis_tdata ;
always @(*)
begin
rden_reg = m_axis_tready&(cnt_data>’d0) ;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rd_addr <= #`U_DLY ‘d0 ;
else if(rden_reg)
rd_addr <= #`U_DLY rd_addr + 1’b1 ;
else keep
end
assign ram_rden = rden_reg ;
assign ram_radr = rd_addr ;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
m_axis_tvalid <= #`U_DLY 1’b0 ;
else if((!m_axis_tvalid)&&rden_reg)
m_axis_tvalid <= #`U_DLY 1’b1 ;
else if((cnt_data==’d0)&&m_axis_tready)
m_axis_tvalid <= #`U_DLY 1’b0 ;
else keep
end
always @(*)
begin
m_axis_tdata = ram_rdat ;
end
dcram_ip
#(
.WIDTH ( WIDTH ) ,
.DEPTH_D ( DEPTH_D )
)
u_dcram_ip(
.clka ( clk ) ,
.wea ( ram_wren ) ,
.addra ( ram_wadr ) ,
.dina ( ram_wdat ) ,
.clkb ( clk ) ,
.enb ( ram_rden ) ,
.addrb ( ram_radr ) ,
.doutb ( ram_rdat )
);
endmodule
//THIS IS UNPUBLISED PROPRIETARY SOURCE CODE of Gaoli.
//The coprright notice above does not evidence any actual of intended
//publication of such source code.
//
//No part of this code may be reproduced,stored in a retrieval system,
//or transmitted,in any form or by any means,electronic,mechanicsal,
//photocopying,recording,or otherwise,without the prior written
//permission of Gaoli.
//
// Project name:
// File name:
// Author: Gao Li
// Dates: 2018.01.20
// Version: V1.0
// Description:
// Called By:
//
//*******************************************************************
`timescale 1ns/1ps
`define U_DLY 1
module dcram_ip
#(
parameter WIDTH = 16 ,
parameter DEPTH_D = 512
)
(
//control signal
clka ,
wea ,
addra ,
dina ,
clkb ,
enb ,
addrb ,
//output data
doutb
);
localparam DEPTH_W = $clog2(DEPTH_D) ;
input clka ;
input wea ;
input [DEPTH_W-1:0 ] addra ;
input [WIDTH-1:0 ] dina ;
input clkb ;
input enb ;
input [DEPTH_W-1:0 ] addrb ;
output [WIDTH-1:0 ] doutb ;
reg [WIDTH-1:0 ] doutb ;
reg [WIDTH-1:0 ] ram_reg [0:DEPTH_D-1 ] ;
always @(posedge clka)
begin
if((wea)&&(~enb))
if((wea))
ram_reg[addra] <= #`U_DLY dina ;
else keep
end
always @(posedge clkb)
begin
if((~wea)&&(enb))
if((enb))
doutb <= #`U_DLY ram_reg[addrb] ;
else keep
end
clka is same to clkb
/*
always @(posedge clka)
begin
if(addra==addrb)
$display(“Write and read error for the dc-RAM”);
end
*/
endmodule