硬件部分

硬件采取6个八位共阳数码管，FPGA对单个数码管的驱动方式是低电平有效。(若移植请注意)

结构图

Verilog代码

顶层测试代码

module top(
    input clk,
    input rst,

    output  [5:0] dig, 
    output  [7:0] dict
);

dig8_6 dig8_6_1(
     .clk(clk),
     .rst(rst),

     .set_data(24'h123456),

     .dig(dig),  //六位独热码表示六个数码管
     .dict(dict) //位选数码管
);
endmodule

6×8位数码管

module dig8_6(
    input clk,
    input rst,

    input [23:0] set_data,//6xh   h=4

    output reg [5:0] dig, //六位独热码表示六个数码管
    output reg [7:0] dict
);

//时钟降频
reg [15:0] cnt1;
always@(posedge clk or negedge rst ) begin
    if(!rst)
        cnt1 <= 16'd0;
    else if (cnt1 <= 16'd50000)
        cnt1 <= cnt1 +1'b1;
    else
        cnt1 <= 16'd0;
end

reg clk_low1;
always@(posedge clk or negedge rst ) begin
    if(!rst)
        clk_low1 <= 1'b0;
    else if (cnt1 <= 16'd24999) begin
        clk_low1 <= 1'b0;
    end
    else
        clk_low1 <= 1'b1;
end


//字典
reg [3:0] data;
always@(posedge clk or negedge rst ) begin
    if(!rst)
        dict <= 8'd0;
    else begin
        case (data)
                4'h0:dict <= 8'b1000000;
                4'h1:dict <= 8'b1111001;
                4'h2:dict <= 8'b0100100;
                4'h3:dict <= 8'b0110000;
                4'h4:dict <= 8'b0011001;
                4'h5:dict <= 8'b0010010;
                4'h6:dict <= 8'b0000010;
                4'h7:dict <= 8'b1111000;
                4'h8:dict <= 8'b0000000;
                4'h9:dict <= 8'b0010000;
                4'ha:dict <= 8'b0001000;
                4'hb:dict <= 8'b0000011;
                4'hc:dict <= 8'b1000110;
                4'hd:dict <= 8'b0100001;
                4'he:dict <= 8'b0000110;
                4'hf:dict <= 8'b0001110;
        endcase
    end
end

//轮流切换数码管
reg [2:0]cnt2;
always@(posedge clk_low1 or negedge rst ) begin
    if(!rst)
        cnt2 <= 3'd0;
    else if (cnt2 < 3'd6)
        cnt2 <= cnt2 +1'b1;
    else
        cnt2 <= 3'd0;
end

always@(posedge clk or negedge rst ) begin
    if(!rst)
        dig <= 6'b111111;
    else 
    begin
        case (cnt2)
        3'd1:dig <= 6'b111110;
        3'd2:dig <= 6'b111101;
        3'd3:dig <= 6'b111011;
        3'd4:dig <= 6'b110111;
        3'd5:dig <= 6'b101111;
        3'd6:dig <= 6'b011111;
        endcase
    end
end

//在切换数码管的同时，赋予位选数据
always@(posedge clk or negedge rst ) begin
    if(!rst)
        data <= 4'd0;
    else 
    begin
        case (dig)
        6'b111110:data <= set_data[3:0];
        6'b111101:data <= set_data[7:4];
        6'b111011:data <= set_data[11:8];
        6'b110111:data <= set_data[15:12];
        6'b101111:data <= set_data[19:16];
        6'b011111:data <= set_data[23:20];
        endcase
    end
end
endmodule

效果图