FPGA之decoder

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实现代码:

module decoder(
   input wire [2:0] a,//三位输入
	
	output reg [7:0] b//八位输出	
);

always@(*)begin//对寄存器类型进行赋值
   case(a)
	   3'b000: b = 8'b1111_1110;
		3'b001: b = 8'b1111_1101;
		3'b010: b = 8'b1111_1011;
		3'b011: b = 8'b1111_0111;
		3'b100: b = 8'b1110_1111;
		3'b101: b = 8'b1101_1111;
		3'b110: b = 8'b1011_1111;
		3'b111: b = 8'b0111_1111;
	   default: b = 8'b0000_0000;
   endcase
end

endmodule

tb文件代码:

`timescale 1ns/1ns
module decoder_tb();
   reg [2:0] a;
   wire [7:0] b;

   decoder dut (
      .a(a),
      .b(b)
   );
   
   initial begin
      a = 3'b000;
      #1;  
      a = 3'b001;
      #1;     
      a = 3'b010;
      #1;
      a = 3'b011;
      #1;      
      a = 3'b100;
      #1;    
      a = 3'b101;
      #1; 
      a = 3'b110;
      #1;    
      a = 3'b111;
      #1;    
   end
   
endmodule



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