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Circuits-Sequential Logic-Finite State Machines（5）

题25：Q3b: FSM

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    reg [2:0]state,next_state;
    always@(*)begin
        case(state)
            3'b000:next_state=x ? 3'b001 : 3'b000;
            3'b001:next_state=x ? 3'b100 : 3'b001;
            3'b010:next_state=x ? 3'b001 : 3'b010;
            3'b011:next_state=x ? 3'b010 : 3'b001;
            3'b100:next_state=x ? 3'b100 : 3'b011;
            default:next_state=3'b000;
        endcase
    end
    always@(posedge clk)begin
        if(reset)
            state<=3'b000;
        else
            state<=next_state;
    end
    always @(posedge clk) begin
        if(reset)
            z<=0;
        else if(next_state==3'b011 |next_state==3'b100)
        	z<=1;
        else 
            z<=0; 
    end
endmodule

题26：Q3c: FSM logic

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
    reg [2:0]Y;
    always@(*)begin
        case(y)
            3'b000:Y=x ? 3'b001 : 3'b000;
            3'b001:Y=x ? 3'b100 : 3'b001;
            3'b010:Y=x ? 3'b001 : 3'b010;
            3'b011:Y=x ? 3'b010 : 3'b001;
            3'b100:Y=x ? 3'b100 : 3'b011;
            default:Y=3'b000;
        endcase
    end

    always @(*) begin
        if(y==3'b011 |y==3'b100)
        	z=1;
        else 
            z=0; 
    end
    assign Y0=Y[0];
endmodule

题27：Q6b: FSM next-state logic

module top_module (
    input [3:1] y,
    input w,
    output Y2);
    reg [2:0]ns;
	parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101;
    always@(*)begin 
        case(y)
        	A:ns=w? A : B;
        	B:ns=w? D : C;
        	C:ns=w? D : E;
            D:ns=w? A : F;
        	E:ns=w? D : E;
        	F:ns=w? D : C;
            default:ns=A;
        endcase
    end      
    assign Y2=ns[1];
endmodule

题28：Q6c: FSM one-hot next-state logic

module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);
    assign Y2=(y[1] & w==0);
    assign Y4=(w & (y[2] | y[3] | y[5] | y[6]));
endmodule

题29：Q6: FSM

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
    reg [2:0]s,ns;
	parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101;
    always@(*)begin 
        case(s)
        	A:ns=w? A : B;
        	B:ns=w? D : C;
        	C:ns=w? D : E;
            D:ns=w? A : F;
        	E:ns=w? D : E;
        	F:ns=w? D : C;
            default:ns=A;
        endcase
    end      
    always@(posedge clk)begin
        if(reset)
            s<=A;
        else 
            s<=ns;
    end
    assign z=(s==E | s==F);    
endmodule

题30：Q2a: FSM

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    input w,
    output z
);
    reg [2:0]s,ns;
	parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101;
    always@(*)begin 
        case(s)
        	A:ns=w? B : A;
        	B:ns=w? C : D;
        	C:ns=w? E : D;
            D:ns=w? F : A;
        	E:ns=w? E : D;
        	F:ns=w? C : D;
            default:ns=A;
        endcase
    end      
    always@(posedge clk)begin
        if(reset)
            s<=A;
        else 
            s<=ns;
    end
    assign z=(s==E | s==F);    
endmodule

题31：Q2b: One-hot FSM equations

module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);
    assign Y1=(w & y[0]);
    assign Y3=(w==0 & (y[1] | y[2] | y[4] | y[5]));
endmodule