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要求：检测连续（连续的意思是间隔不超过150us到230us）两个80us~120us的方波信号

方法：利用上一文的边沿检测方法，当检测到满足条件的脉冲时产生一个标志信号，最后再计算他们的间隔是否满足。

1.检测模块代码如下：

module hyjc(  input clk,
              input clk_3m125,   //3.125mhz
              input data,
				  input rstn,
				  output reg  dout_flag


    );
	 
 
	          reg d1;
				 reg [15:0]cnt=0;
				 reg flag=0;
			always@(posedge clk_3m125)
				 d1<=data;
		assign rising=data&(!d1);
		assign falling=d1&(!data);
				  
                   
			always@(posedge clk_3m125 or negedge rstn)
				 if(!rstn)
				  cnt<=0;
				 else if((rising)&(cnt==0))
				  cnt<=cnt+1;
				 else if((cnt>0)&(falling==0))
					cnt<=cnt+1;
				 else if(falling==1)
					cnt<=0;
					
			always@(posedge clk_3m125)
				 if(cnt<240)
					 flag<=0;
				 else if((cnt>240)&(cnt<360)&(falling))
				   flag<=1;
					
		assign a_flag=flag;
				reg d2;
				reg t_flag=0;
							  
			 always@(posedge clk_3m125)
					 d2<=a_flag;
		assign rising1=a_flag&(!d2);
		assign falling1=d2&(!a_flag);				  
							  
				   reg [15:0]cnt1=0;
						
						
				always@(posedge clk_3m125 or negedge rstn)
					 if(!rstn)
					   cnt1<=0;
					 else if((falling1)&(cnt1==0))
						cnt1<=cnt1+1;
					 else if((cnt1>0)&(rising1==0))
						cnt1<=cnt1+1;
					else if(rising1==1)
						cnt1<=0;
						
					always@(posedge clk_3m125)
						if(cnt1<480)
						  dout_flag<=0;
						else if((cnt1>480)&(cnt1<720)&(rising1==1))
						  dout_flag<=1;
						 else if((cnt1>720)&(rising1==1))
						  dout_flag<=0;
						 else if(cnt1<=0)
						dout_flag<=0;
						
	
endmodule

2.待检测信号模块

module sigproduce(
    input clk,            //50M
	 output clk_3m125,     //3.125mhz
	 output rstn,
    output reg dout     //random squence
    );
  
  wire clk3m125,locked;  
  clockpro u1
   (// Clock in ports
    .CLK_IN1(clk),      // IN
    // Clock out ports
    .CLK_OUT1(clk3m25),     // OUT
    // Status and control signals
    .LOCKED(locked));      // OUT	 
  
  assign clk_3m25 = clk3m125;
  assign rstn = locked;
  
  reg [10:0] cn = 0;	
  always @(posedge clk3m125 or negedge locked)
     if (!locked) begin
        cn <= 0;
        dout <= 0;
        end
     else begin
        cn <= cn + 1;
        case (cn)
			  0: dout <= 0;
			  10: dout <= 1;
			  20: dout <= 0;
			  30: dout <= 1;
			  35: dout <= 0;
			  300: dout <= 1;
			  620: dout <= 0;
			  900: dout <= 1;
			  1250: dout <= 0;
			  1600: dout <= 1;
			  1650: dout <= 0;
        endcase
        end		  
	 

endmodule