With various device technologies, the chip could operate in different modes, such as digital sequential (rowby-row) read-out for near-memory computing, or analog parallel read-out for in-memory computing. In the
simulator, the parameters of synaptic devices and synaptic array modes will be instantiated in param.cpp.
通过各种设备技术，芯片可以以不同的模式运行，如用于近内存计算的数字顺序（行行）读出，或用于内存计算的模拟并行读出。在模拟器中，突触设备的参数和突触阵列模式的参数将在param.cpp中实例化。
一、Parallel Synaptic Array Architectures
并行突触阵列架构
Fig. 9 and Fig. 10 show three kinds of supported synaptic arrays, which could be used to process analog inmemory computing.
9 10 两图表现了三中支持的突触阵列，可以用来模拟存算一体计算
这里的analog不知道啥意思。。。而且经常出现，感觉不是模拟电路里的那个模拟。
对于几个突触阵列，都适用一些假设和设定（assumptions）：
The higher precision than 1-bit in the input neuron activation is represented by multiple cycles of input voltage
signals to the row，
输入neuron activation中的，比1bit更高的精确度，由多个输入电压信号来表示
这里的neuron activation不知道是什么意思，而且反复出现，看看待会能不能搞清楚
and no analog voltage is used to represented the input, thus no digital-to-analog converter (DAC) is used, as the nonlinearity in I-V curve of eNVMs will introduce distortion in parallel read-out
而且，不用模拟电压来表示输入信号，因此，没有使用DAC
因为eNVM的I-V曲线的非线性会引入并行读出的失真
这里还是不知道什么意思
The higher precision than 1-bit in the weight could be represented by a single analog synaptic cell or multiple synaptic cell.
高于1bit的精确度的值，会被标识为一个单纯的analog synaptic 或者多重analog synaptic
还是不知道什么意思
For example, 8-bit weight could be represented a single 8-bit eNVM cell (assuming it is technologically viable), or 2 eNVM cells (4 bits per cell), or 4 eNVM cells (2 bits per cell), or 8 eNVM binary cells.
例如，8bit的值，会被表示为一个单纯的8-bit eNVM cell，或者两个2 eNVM cells，或者。。。
差不多可以理解为一个器件可以表示多bit的值
In our design, the inference is performed in parallel mode by activating all the rows, while the weight update in the training is performed in a row-by-row fashion.
在我们的设计中，推理是通过激活所有行来以并行模式执行的，而训练中的权重更新是以逐行的方式执行的。
不太懂什么意思。。。。
It should be noted that as the peripheral ADC size is typically much larger than the column pitch of the array, therefore column sharing is used by the column mux (e.g. 8 columns share one ADC).
需要注意的是，由于外围ADC的大小通常远远大于阵列的列间距，因此列mux使用列共享(例如，8列共享一个ADC)。
这里也不太懂，总之是有个共享原理
1、SRAM synaptic array SRAM突触阵列
Multiple digital SRAM cells can be grouped along the row to represent one weight with higher precision than 1-bit, as shown in Fig. 9.
多重数字SRAMcell，可以串联成一行，来表示一个精确度超过1bit的权值
The weighted sum and weight update operations are similar to the row-by-row read and write operations in conventional SRAM for memory, respectively.
权值相加和权值更新操作，和传统SRAM中的row by row 读写操作类似。
In sequential-read-out mode as Fig. 9 (a) shows, to select a row, the WL is activated through the WL decoder.
在串行读出模式中，如图所示。9(a)显示，要选择一行，WL通过WL解码器激活WL。
To access all the cells on the selected row, the BLs are pre-charged by the pre-charger and the write driver in weighted sum and weight update, respectively.
为了访问所选行上的所有单元格，bl分别由预充电器和写入驱动器以加权和和重量更新进行预充电。
After the memory data are read by the sense amplifier (S/A), the adder and register are used to accumulate the partial weighted sum in a row-by-row fashion.
在由感知放大器（S/A）读取存储器数据后，使用加法器和寄存器以逐行方式累加 部分加权和partial weighted sum。
In parallel-read-out mode as demonstrated in [10], the input vectors will be fetched in via WL switch matrix, the partial-sums will be collected along columns simultaneously at one time with high-precision flash-ADCs based on multilevel S/A by varying references.
在并行读出模式中，则有不同的操作
还使用了ADC
不知道这里并行和串行有什么区别
以及 sense amplifier 和ADC的区别
2、Analog eNVM 1T1R synaptic array
Fig. 10 (a) and (b) shows the structure of 1T1R based eNVM array.
10图展示了1T1R的eNVM阵列结构。
这里很重要，学长讲过这里
The WL controls the gate of the transistor, which can be viewed as a switch for the cell.
The source line (SL) connects to the source of the transistor.
栅极作为开关，WL控制
SL连接源级
The eNVM cell’s top electrode connects to the BL, while its bottom electrode connects to the drain of the transistor through a contact via.
eNVM上下极连接相应的位置
In such case, the cell area of 1T1R array is then determined by the transistor size, which is typically >6F2 depending on the maximum current required to be delivered into the eNVM cell.
这种情况下，阵列的单元的面积，由晶体管transistor 面积决定，通常大于这个值（？）
取决于需要传输进eNVM cell的最大需要电流
Larger current needs larger transistor gate width/length (W/L).
大电流需要大的宽长比
However, conventional 1T1R array is not able to perform the parallel weighted sum operation.
然而，传统的1T1R array无法实现并行权值相加操作
To solve this problem, we modify the conventional 1T1R array by rotating the BLs by 90o, which is known as the pseudo-crossbar array architecture, as shown in Fig. 11 (b).
为了解决此问题，我们更改了传统1T1R array，把BL线旋转90度，被称为伪crossbar array结构
至于什么是crossbar array结构，我也不知道。。。
In weighted sum operation, all the transistors will be transparent when all WLs are turned on. Thus, the input vector voltages are provided to the BLs, and the weighted sum currents are read out through SLs in parallel. Then the weighted sum currents are digitalized by a current-mode sense amplifier (S/A), and a Flash-ADC with multilevel S/A by varying references.
在权值相加操作中，所有的晶体管在WL开启下导通
因此，输入电压向量作用在BL上，总电流被并行读出
然后，总电流被数字化，通过S/A和ADC
3、Analog eNVM crossbar array
模拟eNVM crossbar 阵列
The crossbar array structure has the most compact and simplest array structure for analog eNVM devices to form a weight matrix, where each eNVM device is located at the cross point of a word line (WL) and a bit line (BL), as shown in Fig. 10 ©.
crossbar 阵列结构，有着最紧凑和最简单的阵列结构，对于用模拟eNVM设备来形成一个权重矩阵
其中，每个eNVM设备都位于字线(WL)和位线(BL)的交叉点上，如图所示。
The crossbar array structure can achieve a high integration density of 4F2/cell (F is the lithography feature size).
crossbar 阵列结构可以实现4F2/单元的高集成密度（F为光刻特征尺寸）。
If the input vector is encoded by read voltage signals, the weighted sum operation (matrix-vector multiplication) can be performed in a parallel fashion with the crossbar array.
如果输入向量由读取电压信号进行编码，则可以与横条阵列并行地执行加权和运算（矩阵向量乘法）。
不知道什么叫input vector is encoded by read voltage signals
Here, the crossbar array assumes there is an ideal two-terminal selector device connected to each eNVM, which is desired for suppressing the sneak path currents during the row-by-row weight update. It should be noted that ideal selector device is still under research and development.
在这里，横条阵列假设有一个理想的双端选择器设备连接到每个eNVM，这是为了在逐行权重更新期间抑制泄露路径电流。需要注意的是，理想的选择器装置仍在研发之中。
问题：权重更新是什么操作 以及 选择器放在了哪里，为什么是双端？难道是晶体管？
4、Analog FeFET array 模拟铁电阵列
As shown in Fig. 10 © and (d), the analog FeFET array is in the pseudo-crossbar fashion as proposed in [11], which is similar to the analog eNVM pseudo-crossbar one.
如图所示。10©和(d)，模拟FeFET阵列采用[11]中提出的伪交叉方式，类似于模拟eNVM伪交叉阵列。
It also has an access transistor for each cell to prevent programming on other unselected rows during row-by-row weight update.
仍然是同一个问题，什么是weight update
As FeFET is a three-terminal device, it needs two separate input signals to be fetched to activate WLs and introduce read voltages to RS (read select), respectively, where RS is used to fetch in input vectors as Fig. 12 shown below.
由于铁电FET是三端器件，需要两个分立的输入信号，来激活WL、RS
RS是用来取来输入信号的
二、 Array Peripheral Circuits
阵列外围电路
这里介绍了9种阵列外围电路，需要一个一看看，有哪些外围电路。
这里可能就有很多熟悉的内容了。
不过时间有限，有空再细说。。。
1、Level shifter
电平转换
Level-shifter is normally required for RRAM (or PCM/FeFET) array to support the need of higher write
voltage (e.g. >1.5V which is higher than logic VDD). In the simulator, we take a conventional level shifter
as shown in Figure.13. If the validation mode is selected, a wiring area factor α = 1.44 will be imposed on
this module for calibration.
RRAM(或PCM/FeFET)阵列通常需要电平移位器，以支持需要更高的写入电压(例如>1.5V，高于逻辑VDD)。在模拟器中，我们采用一个传统的电平移器，如图所示。13.如果选择了验证模式，将在该模块上施加一个布线面积因子α=1.44以进行校准。
2、Switch matrix
开关矩阵
Switch matrices are used for fully parallel voltage input to the array rows or columns.
开关矩阵是用来完全地使 输入电压 并行到 阵列的行和列。不懂。。。
3、 Crossbar WL decoder
Crossbar WL解码器
4、 Decoder driver
解码器驱动
5、 New Decoder Driver and Switch Matrix
新解码器驱动 和 开关矩阵
6、 Multiplexer (Mux) and Mux decoder
多路复用器(Mux)和Mux解码器
7、 Analog-to-digital converter (ADC)
ADC不用多说
8、 Adder and register
加法器和寄存器
9、 Adder and shift register
加法 和 转换寄存器
很细节这部分，有空再看。争取能把 突触阵列（synaptic arrays） 基本的架构搭建起来